74LVC1G125SE-7 Diodes Incorporated IC BUF NON-INVERT 5.5V SOT353

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2024/08/23 225
74LVC1G125SE-7 Diodes Incorporated  IC BUF NON-INVERT 5.5V SOT353


• Wide Supply Voltage Range from 1.65 to 5.5V
• ± 24mA Output Drive at 3.3V
• CMOS Low Power Consumption
• IOFF Supports Partial-Power-Down Mode Operation
• Inputs Accept Up to 5.5V
• ESD Protection Tested per JESD 22 Exceeds 200-V Machine Model (A115) Exceeds 2000-V Human Body Model (A114) Exceeds 1000-V Charged Device Model (C101)
• Latch-Up Exceeds 100mA per JESD 78, Class I
• Range of Package Options
• Direct Interface with TTL Levels
• Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)


CATALOG
74LVC1G125SE-7 PARAMETRIC INFO
74LVC1G125SE-7 PACKAGE INFO
74LVC1G125SE-7 MANUFACTURING INFO
74LVC1G125SE-7 PACKAGING INFO
74LVC1G125SE-7 APPLICATIONS


PARAMETRIC INFO
Process Technology CMOS
Logic Family LVC
Logic Function Buffer/Line Driver
Input Signal Type Single-Ended
Output Type 3-State
Polarity Non-Inverting
Tolerant I/Os (V) 5.5 Inputs
Bus Hold No
Number of Elements per Chip 1
Number of Channels per Chip 1
Number of Output Enables per Chip 1 Low
Number of Input Enables per Chip 0
Number of Inputs per Chip 1
Number of Outputs per Chip 1
Minimum Operating Supply Voltage (V) 1.65
Maximum Operating Supply Voltage (V) 5.5
Typical Operating Supply Voltage (V) 1.8|2.5|3.3|5
Minimum Operating Temperature (°C) -40
Maximum Operating Temperature (°C) 125
Minimum Storage Temperature (°C) -65
Maximum Storage Temperature (°C) 150
Maximum Propagation Delay Time @ Maximum CL (ns) 2.5(Typ)@2.7V|2.1(Typ)@3.3V|1.7(Typ)@5V
Absolute Propagation Delay Time (ns) 12
Propagation Delay Test Condition (pF) 50
Maximum High Level Output Current (mA) -32
Maximum Low Level Output Current (mA) 32
Maximum Quiescent Current (uA) 200
Typical Quiescent Current (uA) 0.1


PACKAGE INFO
Supplier Package SOT-353
Basic Package Type Lead-Frame SMT
Pin Count 5
Lead Shape Gull-wing
PCB 5
Tab N/R
Pin Pitch (mm) 0.65
Package Length (mm) 2.15
Package Width (mm) 1.3
Package Height (mm) 0.95
Package Diameter (mm) N/R
Seated Plane Height (mm) 1
Mounting Surface Mount
Package Material Plastic
Package Description Small Outline Transistor
Package Family Name SOT
Package Outline Link to Datasheet


MANUFACTURING INFO
MSL 1
Maximum Reflow Temperature (°C) 260
Reflow Solder Time (Sec) 30
Number of Reflow Cycle 3
Standard J-STD-020D
Reflow Temp. Source Link to Datasheet
Maximum Wave Temperature (°C) N/R
Wave Solder Time (Sec) N/R
Lead Finish(Plating) Matte Sn annealed
Under Plating Material N/A
Terminal Base Material N/A


PACKAGING INFO
Packaging Suffix 7
Packaging Tape and Reel
Quantity Of Packaging 3000
Packaging Document Link to Datasheet


APPLICATIONS
• Voltage Level Shifting
• General Purpose Logic
• Power Down Signal Isolation
• Wide Array of Products Such as:PCs, Networking, Notebooks, Netbooks, PDAs Tablet Computers, E-readers Computer Peripherals, Hard Drives, CD/DVD ROMs TVs, DVDs, DVRs, Set Top Boxes Cell Phones, Personal Navigation / GPS MP3 Players, Cameras, Video Recorders

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