S25FL128SAGMFIR01 Infineon Technologies IC FLASH 128M SPI 133MHZ 16SOIC

label:

2024/01/19 439

• CMOS 3.0 V core with versatile I/O

• SPI with multi-I/O
- SPI clock polarity and phase modes 0 and 3
- DDR option - Extended addressing: 24- or 32-bit address options
- Serial command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families
- Multi I/O command set and footprint compatible with S25FL-P SPI family

• READ commands
- Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
- AutoBoot - Power up or reset and execute a Normal or Quad read command automatically at a preselected address
- Common flash interface (CFI) data for configuration information

• Programming (1.5 MBps)
- 256- or 512-byte page programming buffer options
- Quad-input page programming (QPP) for slow clock systems
- Automatic ECC-internal hardware error correction code generation with single bit error correction

• Erase (0.5 to 0.65 MBps)
- Hybrid sector size option- Physical set of thirty two 4-KB sectors at top or bottom of address space with all remaining sectors of 64 KB, for compatibility with prior generation S25FL devices.
- Uniform sector option- always erase 256-KB blocks for software compatibility with higher density and future devices.

• Cycling endurance
- 100,000 program-erase cycles, minimum

• Data retention
- 20 year data retention, minimum

• Security features
- OTP array of 1024 bytes
- Block protection
• Status Register bits to control protection against program or erase of a contiguous range of sectors.
• Hardware and software control options
- Advanced sector protection (ASP)
• Individual sector protection controlled by boot code or password

• 65-nm MIRRORBIT™ technology with Eclipse architecture

• I/O supply voltage: 1.65 V to 3.6 V
- SO16 and FBGA packages

CATALOG

S25FL128SAGMFIR01 COUNTRY OF ORIGIN

S25FL128SAGMFIR01 PARAMETRIC INFO

S25FL128SAGMFIR01 PACKAGE INFO

S25FL128SAGMFIR01 MANUFACTURING INFO

S25FL128SAGMFIR01 PACKAGING INFO

S25FL128SAGMFIR01 ECAD MODELS

S25FL128SAGMFIR01 FUNCTIONAL BLOCK DIAGRAM

COUNTRY OF ORIGIN

China

Thailand

Taiwan (Province of China)

United States of America

Philippines

PARAMETRIC INFO

Density (bit)	128M
Cell Type	NOR
Interface Type	Serial (SPI, Dual SPI, Quad SPI)
Block Organization	Symmetrical
Boot Block	Yes
Timing Type	Synchronous
Architecture	Sectored
Maximum Access Time (ns)	14.5
Typical Operating Supply Voltage (V)	3\|3.3
Programmability	Yes
I/O Mode	Serial
Minimum Operating Temperature (°C)	-40
Maximum Operating Temperature (°C)	85
Supplier Temperature Grade	Industrial
Number of Bits per Word (bit)	1/2/4
Number of Words	128M/64M/32M
Location of Boot Block	Bottom\|Top
Maximum Operating Current (mA)	100
Programming Voltage (V)	2.7 to 3.6
Maximum Operating Frequency (MHz)	133
Sector Size	64Kbyte x 256
Program Current (mA)	100
Address Bus Width (bit)	32
Minimum Operating Supply Voltage (V)	2.7
Maximum Operating Supply Voltage (V)	3.6
Maximum Erase Time (s)	165/Bulk
Maximum Programming Time (ms)	0.75/Page
Command Compatible	Yes
ECC Support	Yes
Erase Suspend/Resume Modes Support	Yes
Simultaneous Read/Write Support	No
Support of Common Flash Interface	Yes
Support of Page Mode	No
Page Size	256byte\|512byte
Minimum Endurance (Cycles)	100000
Minimum Storage Temperature (°C)	-65
Maximum Storage Temperature (°C)	150
Density in Bits (bit)	134217728
Process Technology	65nm, MirrorBit

PACKAGE INFO

Supplier Package	SOIC W
Basic Package Type	Lead-Frame SMT
Pin Count	16
Lead Shape	Gull-wing
PCB	16
Tab	N/R
Pin Pitch (mm)	1.27
Package Length (mm)	10.3
Package Width (mm)	7.5
Package Height (mm)	2.55(Max)
Package Diameter (mm)	N/R
Seated Plane Height (mm)	2.65(Max)
Mounting	Surface Mount
Package Weight (g)	N/A
Package Material	Plastic
Package Description	Small Outline IC Wide Body
Package Family Name	SO
Jedec	MS-013AA
Package Outline	Link to Datasheet

MANUFACTURING INFO

MSL	3
Maximum Reflow Temperature (°C)	260
Reflow Solder Time (Sec)	30
Number of Reflow Cycle	3
Standard	J-STD-020D
Reflow Temp. Source	Link to Datasheet
Maximum Wave Temperature (°C)	N/R
Wave Solder Time (Sec)	N/R
Lead Finish(Plating)	Matte Sn annealed
Under Plating Material	Ag
Terminal Base Material	Cu Alloy
Number of Wave Cycles	N/R

PACKAGING INFO

Packaging Suffix	1
Packaging	Tube
Quantity Of Packaging	1
Packaging Document	Link to Datasheet

ECAD MODELS

FUNCTIONAL BLOCK DIAGRAM