XC9572XL-10TQG100I Xilinx IC CPLD 72MC 10NS 100TQFP

label:

2023/11/7 396

• Optimized for high-performance 3.3V systems
- 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz
- Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)
- Pb-free available for all packages
- Lower power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS FastFLASH technology

• Advanced system features
- In-system programmable
- Superior pin-locking and routability with FastCONNECT II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with individual product-term allocation
- Local clock inversion with three global and one product-term clocks
- Individual output enable per output pin with local inversion
- Input hysteresis on all user and boundary-scan pin inputs
- Bus-hold circuitry on all user pin inputs
- Supports hot-plugging capability
- Full IEEE Std 1149.1 boundary-scan (JTAG) support on all devices

• Four pin-compatible device densities
- 36 to 288 macrocells, with 800 to 6400 usable gates

• Fast concurrent programming

• Slew rate control on individual outputs

• Enhanced data security features

• Excellent quality and reliability
- 10,000 program/erase cycles endurance rating
- 20 year data retention

• Pin-compatible with 5V core XC9500 family in common package footprints

CATALOG

XC9572XL-10TQG100I COUNTRY OF ORIGIN

XC9572XL-10TQG100I PARAMETRIC INFO

XC9572XL-10TQG100I PACKAGE INFO

XC9572XL-10TQG100I MANUFACTURING INFO

XC9572XL-10TQG100I ECAD MODELS

COUNTRY OF ORIGIN

Korea (Republic of)

Philippines

Taiwan (Province of China)

PARAMETRIC INFO

Device System Gates	1600
Number of User I/Os	72
Number of Logic Blocks/Elements	4
Number of Macro Cells	72
Number of Product Terms per Macro	90
Number of Inter Dielectric Layers	4
Number of Flip Flops	72
Tradename	XC9500
Copy Protection	Yes
Number of Global Clocks	3
Program Memory Type	Flash
Family Name	XC9500
Process Technology	0.35um, CMOS
Speed Grade	10
Data Gate	No
Individual Output Enable Control	Yes
Programmability	Yes
In-System Programmability	Yes
Reprogrammability Support	No
Maximum Internal Frequency (MHz)	100
Maximum Operating Frequency (MHz)	100
Maximum Clock to Output Delay (ns)	5.8
Maximum Operating Current (mA)	20(Typ)
Maximum Propagation Delay Time (ns)	10
Tolerant Configuration Interface Voltage (V)	5
I/O Voltage (V)	2.5\|3.3
Minimum Operating Supply Voltage (V)	3
Typical Operating Supply Voltage (V)	3.3
Programmable Type	In System Programmable
Maximum Operating Supply Voltage (V)	3.6
Minimum Operating Temperature (°C)	-40
Maximum Operating Temperature (°C)	85
Temperature Flag	Opr
Supplier Temperature Grade	Industrial
Minimum Storage Temperature (°C)	-65
Maximum Storage Temperature (°C)	150

PACKAGE INFO

Supplier Package	TQFP
Basic Package Type	Lead-Frame SMT
Pin Count	100
Lead Shape	Gull-wing
PCB	100
Tab	N/R
Pin Pitch (mm)	0.5
Package Length (mm)	14
Package Width (mm)	14
Package Height (mm)	1.4
Package Diameter (mm)	N/R
Seated Plane Height (mm)	1.6(Max)
Mounting	Surface Mount
Package Material	Plastic
Package Description	Thin Quad Flat Package
Package Family Name	QFP
Jedec	MS-026BED
Package Outline	Link to Datasheet

MANUFACTURING INFO

MSL	3
Maximum Reflow Temperature (°C)	260
Reflow Solder Time (Sec)	30
Number of Reflow Cycle	3
Reflow Temp. Source	Link to Datasheet
Maximum Wave Temperature (°C)	N/R
Wave Solder Time (Sec)	N/R
Wave Temp. Source	Link to Datasheet
Lead Finish(Plating)	Matte Sn annealed
Under Plating Material	N/A
Terminal Base Material	Cu

ECAD MODELS